1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device that has a pipeline structure, and performs a data-dependent operation, with a capability of realizing low power consumption, and a clock control method for the semiconductor integrated circuit device.
2. Description of the Related Art
Recently, with an increase of speed and scale of a semiconductor integrated circuit device, there has been a growing demand for lower power consumption. A clock gating technology is generally used as one of approaches to reducing the power consumption of the semiconductor integrated circuit device.
A technology that applies the clock gating technology to a processor is disclosed in JP-A H11-167629 (KOKAI), which relates to a processor having a data-dependent clock gating function. The processor includes a process control unit that controls the start of operation, a plurality of operation units each performing an actual processing, and a clock control unit that supplies a clock to each of the operation units. The operation units are connected in a pipeline structure. When receiving an operation start signal from the process control unit, each of the operation units enables a request signal for requesting a clock supply to the clock control unit, and when the operation ends, disables the request signal. The clock control unit supplies a clock signal to each of the operation units only when the request signal from the operation unit is enabled.
Hai Li, et al., “Deterministic Clock Gating for Microprocessor Power Reduction”, Proceedings of the HPCA-9, 2003 discloses a clock gating technology for a pipeline structure of a processor, in which the clock gating technology is applied by using a plurality of stages of the pipeline structure of a processor as an area of clock supply. It is determined by decoding a corresponding part in an execution command whether to provide clock supply to each clock supply area. For example, when a clock supply area inside the processor is divided into a command fetching unit, a command decoding unit, an integer operation unit, a floating-point operation unit, and a memory writing-back unit, to execute a floating-point operation instruction, clock supply to a computing unit for integer operation is stopped, and to execute a branch instruction, clock supply to the floating-point operation unit and to the memory writing-back unit is stopped.
However, according to the technology disclosed in JP-A H11-167629 (KOKAI), the process control unit controls all of the operation units, so that the circuits become complicated. Moreover, the process control unit individually controls settings and the start of processing each of the operation units, so that control of clock supply to each of the operation units is individually processed, consequently, each of the operation units needs a separated clock control unit. For this reason, because of complication of the control unit and increase in the number of units, power consumption by the processor is increased.
According to the literature by Hai Li, et al., processing for clock control, such as decoding of a command, needs to be performed with respect to each supply area of the same clock in the processor. For this reason, if a clock supply area is divided into small areas, such as stages of the pipeline, it results in increase in power consumption by the processor in turn.